SRC Proposal (“Hardware Security (HWS) Solicitation”) August 2024

Lifecycle Security Assurance for 2.5D/3D Heterogeneously Integrated Systems

References

  1. “Semiconductor Research Corporation Microelectronics and Advanced Packaging Technology Roadmap.” SRC MAPT. [Online; accessed 2024/04/22].
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  3. J. Talukdar, A. Chaudhuri, J. Kim, S. K. Limt, and K. Chakrabarty, “Securing heterogeneous 2.5 d ics against ip theft through dynamic interposer obfuscation,” in 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1–2, IEEE, 2023.
  4. M. S. M. Khan, C. Xi, M. S. U. Haque,  M. M. Tehranipoor,  and N. Asadizanjani,  “Exploring ad- vanced packaging technologies for reverse engineering a system-in-package (SIP),” IEEE Transactions on Components, Packaging and Manufacturing Technology, 2023.
  5. J. Talukdar, A. Vyas, and K. Chakrabarty, “Detection of voltage droop-induced timing fault attacks due to hardware trojans,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024.
  6. J. Talukdar, S. Chen, A. Das, S. Aftabjahani, P. Song, and K. Chakrabarty, “A BIST-based dynamic obfuscation scheme for resilience against removal and oracle-guided attacks,” in 2021 IEEE International Test Conference (ITC), pp. 170–179, 2021.
  7. M. S. U. I. Sami, H. M. Kamali, , F. Farahmandi, F. Rahman, and M. Tehranipoor, “Enabling security of heterogeneous integration: From supply chain to in-field operations,” IEEE Design & Test, vol. 40, no. 5, pp. 86–95, 2023.
  8. N. Vashistha, M. L. Rahman, M. S. U. Haque, A. Uddin, M. S. U. I. Sami, A. M. Shuo, P. Calzada, F. Farahmandi, N. Asadizanjani, F. Rahman, and M. Tehranipoor, “ToSHI – towards secure heteroge- neous integration: Security risks, threat assessment, and assurance.” Cryptology ePrint Archive, Paper 2022/984, 2022. https://eprint.iacr.org/2022/984.
  9. H. Park, J. Kim, V. C. K. Chekuri, M. A. Dolatsara, M. Nabeel, A. Bojesomo, S. Patnaik, O. Sinanoglu, M. Swaminathan, S. Mukhopadhyay,  J. Knechtel,  and S. K. Lim,  “Design flow for active interposer- based 2.5-d ics and study of risc-v architecture with secure noc,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 10, no. 12, pp. 2047–2060, 2020.
  10. I. Lee, M. Cheong, and S. Kang, “Highly reliable redundant tsv architecture for clustered faults,” IEEE Transactions on Reliability, vol. 68, no. 1, pp. 237–247, 2019.
  11. J. Talukdar, A. Chaudhuri, and K. Chakrabarty, “Taintlock: Preventing IP theft through lightweight dynamic scan encryption using taint bits,” in 2022 IEEE European Test Symposium (ETS), pp. 1–6, IEEE, 2022.
  12. J. Talukdar, A. Chaudhuri, E. Ortega, and K. Chakrabarty, “Taintlock: Hardware IP protection against oracle-guided and oracle-reconstruction attacks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024.
  13. J. Talukdar, W.-H. Paik, E. Ortega, and K. Chakrabarty, “Alt-lock: Logic and timing ambiguity-based IP obfuscation against reverse engineering,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2024.
  14. E. Ortega, J. Talukdar, W. Paik, F. Su, Chattopadhyay, and K. Chakrabarty, “E-SCOUT: Efficient spa- tial clustering-based outlier detection through telemetry,” in 2024 IEEE International Test Conference, 2024.
  15. J. Talukdar, S. Chen, A. Das, S. Aftabjahani, P. Song, and K. Chakrabarty, “A BIST-based dynamic obfuscation scheme for resilience against removal and oracle-guided attacks,” in 2021 IEEE International Test Conference (ITC), pp. 170–179, IEEE, 2021.