SRC White Paper (“Computer-Aided Design and Test (CADT) Solicitation”) June 2024 

SHAD-LLS: Streamlining Heterogeneous 3D AI Accelerator Design with LLMs and Symbolic AI

References

  1. [1] Liu, Mingjie, Teodor-Dumitru Ene, Robert Kirby, Chris Cheng, Nathaniel Pinckney, Rongjian Liang, Jonah Alben et al. “Chipnemo: Domain-adapted llms for chip design.” arXiv preprint arXiv:2311.00176 (2023).
  2. [2] Thakur, S., Ahmad, B., Pearce, H., Tan, B., Dolan-Gavitt, B., Karri, R. and Garg, S., 2024. Verigen: A large language model for verilog code generation. ACM Transactions on Design Automation of Electronic Systems29(3), pp.1-31.
  3. [3] Zhong, R., Du, X., Kai, S., Tang, Z., Xu, S., Zhen, H.L., Hao, J., Xu, Q., Yuan, M. and Yan, J., 2023. LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation. arXiv preprint arXiv:2401.12224.
  4. [4] Fang, W., Li, M., Li, M., Yan, Z., Liu, S., Zhang, H. and Xie, Z., 2024. AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs. arXiv preprint arXiv:2402.00386.
  5. [5] Xu, K., Sun, J., Hu, Y., Fang, X., Shan, W., Wang, X. and Jiang, Z., 2024. MEIC: Re-thinking RTL Debug Automation using LLMs. arXiv preprint arXiv:2405.06840.