White Paper Submitted to SRC (“Computer Aided Design and Test (CADT) Solicitation”), June 2024

Fault-Tolerant Systolic Array-Based AI Accelerators

References

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  2. A. Chaudhuri, C.-Y. Chen and K. Chakrabarty, “Recent advances in testing techniques for AI hardware accelerators”, Foundations and Trends in Integrated Circuits and Systems, vol. 2, pp. 244–380, 2023.
  3. A. Chaudhuri, J. Talukdar, J. Jung, G.-J. Nam and and K. Chakrabarty, “Fault criticality assessment for AI accelerators using graph convolutional networks”, Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, 2021.
  4. A. Chaudhuri, C.-Y. Chen, J. Talukdar, S. Madala, A. K. Dubey and K. Chakrabarty, “Efficient fault-criticality analysis for AI accelerators using a neural twin”, Proc. IEEE International Test Conference, 2021.
  5. A. Chaudhuri, C.-Y. Chen, J. Talukdar and K. Chakrabarty, “Functional test generation for AI accelerators using Bayesian optimization”, IEEE VLSI Test Symposium, 2023.
  6. Zhao, Yingnan, Ke Wang, and Ahmed Louri, “FSA: An efficient fault-tolerant systolic array-based DNN accelerator architecture”, IEEE International Conference on Computer Design (ICCD), pp. 545-552. 2022.
  7. Lee, Hayoung, Jihye Kim, Jongho Park, and Sungho Kang. “STRAIT: Self-test and Self-recovery for AI Accelerator”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, pp. 3092-3104, September 2023.