List of PhD Dissertations

The graduate student PhD theses are listed below (in reverse chronological order).

  1. Jayeeta Chaudhuri, “From Threats to Trust: Security Strategies for FPGAs and Analog/Mixed-Signal Circuit Design”, September 2025; First position: DFT Methodology Engineer, NVIDIA, Santa Clara, CA.
  2. Shiyi Jiang, “Towards Personalized, Privacy-preserving, and Explainable AI for Healthcare”, November 2024; First position: Postdoctoral researcher. Department of Biomedical Informatics, Columbia University.
  3. Aritra Ray, “Applications of Predictive Analytics for Machine Learning as a Service”, November 2024; First position: Hardware Engineer 2, Microsoft, Redmond, WA.
  4. Wei-Kai Liu, “Algorithms and Architectures for Resilient Hardware Design”, November 2024; First position: Design for Test Engineer, Apple, Cupertino, CA.
  5. Jin Zhou, “Integration of Hand-Crafted Features and Deep Learning for Imaging Application in Precision Medicine”, September 2024; First position: Research Scientist, Meta, Menlo Park, CA.
  6. Jonti Talukdar, “Preventing IP Theft in Heterogeneous 2.5D/3D Integrated Circuits”, June 2024; First position: Senior DFX Engineer, NVIDIA, Santa Clara, CA.
  7. Shao-Chun Hung, “Testing and Fault Diagnosis Solutions for Monolithic 3D ICs”, March 2024; First position: Senior DFT Engineer, NVIDIA, Santa Clara, CA.
  8. Arjun Chaudhuri, “Fault Modeling, Design-for-Test, and Fault Tolerance for Machine Learning Hardware”, November 2022; First position: DFX Methodology Engineer, NVIDIA, Santa Clara, CA.
  9. Sanmitra Banerjee, “Modeling and Optimization of Emerging Technology-Based Artificial Intelligence Accelerators under Imperfections”, May 2022; First position: DFT Engineer, NVIDIA, Santa Clara, CA.
  10. Tung-Che Liang, “Security and Synthesis Solutions for Digital Microfluidic Biochips”, June 2021; First position: DFT Engineer, NVIDIA, Santa Clara, CA.
  11. Rana Elnaggar, “Security and Survivability of Heterogeneous SoCs”, August 2020; First position: Security Researcher, Intel Corporation, Santa Clara, CA.
  12. Mengyun Liu, “Adaptive Methods for Machine Learning-Based Testing of Integrated Circuits and Boards”, June 2020; First position: DFT Engineer, NVIDIA, Santa Clara, CA.
  13. Zhanwei Zhong, “Design, Optimization and Test Methods for Robust Digital Microfluidics Biochips”, May 2020; First position: Senior Design Verification Engineer, Marvell Semiconductor, Santa Clara, CA.
  14. Abhishek Koneru, “Test and Design-for-Testability Solutions for Monolithic 3D Integrated Circuits”, January 2019; First position: DFT Engineer, Apple, Cupertino, CA.
  15. Shi Jin, “Anomaly-Detection and Health-Analysis Techniques for Core Router Systems”, June 2018; First position: Senior DFT Engineer, NVIDIA, Santa Clara, CA.
  16. Mohamed Ibrahim, “Optimization of Trustworthy Biomolecular Quantitative Analysis Using Cyber-Physical Microfluidic Platforms”, May 2018; First position: SoC Design Engineer, Intel Corporation, Santa Clara, CA.
  17. Zipeng Li, “Design, Optimization, and Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochips”, April 2017; First position: DFT Engineer, Intel Corporation, Santa Clara, CA.
  18. Ran Wang, “Testing of Interposer-Based 2.5D Integrated Circuits”, March 2016; First position: Senior DFT Engineer, NVIDIA, Santa Clara, CA.
  19. Kai Hu, “Optimization, Testing and Design-for-Testability of Flow-Based Microfluidic Biochips”, June 2015; First position: Senior Hardware Engineer, Oracle, Santa Clara, CA.
  20. Sergej Deutsch, “Test and Debug Solutions for 3D-Stacked Integrated Circuits”, April 2015; First position: Research Scientist, Intel Labs, Hillsboro, OR.
  21. Tong Zhou, “Data Collection, Dissemination, and Security in Vehicular Ad Hoc Network”, December 2014; First position: Software Engineer, NetApp, Research Triangle Park, NC.
  22. Mukesh Agrawal, “Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs”, December 2014; First position: Performance Architect, Intel Corporation, Hillsboro, OR.
  23. Fangming Ye, “Knowledge-Driven Board-Level Functional Fault Diagnosis”, August 2014; First position: Senior Hardware Engineer, Qualcomm, San Jose, CA.
  24. Qing Duan, “Real-Time and Data-Driven Operation Optimization and Knowledge Discovery for an Enterprise Information System”, June 2014; First position: Data Scientist, PayPal, San Jose, CA.
  25. Brandon Noia, “Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs”, March 2014; First position: Senior Design Engineer, AMD, Boxborough, MA.
  26. Yan Luo, “Design and Optimization Methods for Pin-Limited and Cyberphysical Digital Microfluidic Biochips”, November 2013; First position: Senior Hardware Engineer, Oracle Corporation, Santa Clara, CA.
  27.  Zhaobo Zhang, “Optimization of Fault-Insertion Test and Diagnosis of Functional Failures”, June 2011; First position: Senior Hardware Engineer, Huawei Technologies, Santa Clara, CA.
  28. Hongxia Fang, “Design-for-Testability and Diagnosis Methods to Target Unmodeled Defects in Integrated Circuits and Multi-Chip Boards”, April 2011; First position: Senior Member of Technical Staff, Cadence Design Systems, Endicott, NY.
  29. Yang Zhao, “Unified Design and Optimization Tools for Digital Microfluidic Biochips”, February 2011; First position: ASIC DFT Design Engineer, AMD, Boston, MA.
  30. Harshavardhan Sabbineni, “Location-Aware Protocols for Energy-Efficient Information Processing in Wireless Sensor Networks”, May 2009; First position: Senior Member of Technical Staff, Oracle Corporation, CA.
  31. Mahmut Yilmaz, “Automated Test Grading and Pattern Selection for Small-Delay Defects”, April 2009; First Position: Senior Design Engineer, AMD, Sunnyvale, CA.
  32. Tao Xu, “Optimization Tools for the Design of Reconfigurable Digital Microfluidic Biochips”, December 2008; First Position: Hardware Engineer IV, Cisco Systems, Inc., Research Triangle Park, NC.
  33. Sudarshan Bahukudumbi, “Wafer-Level Testing and Test Planning for Integrated Circuits”, April 2008; First Position: Quality and Reliability Test Engineer, Intel Corporation, Hillsborough, OR, and Penang, Malaysia.
  34. Zhanglei Wang, “Techniques for Reducing Manufacturing Test Cost: Test Pattern Selection, Test Compression, and Test Scheduling”, March 2007; First Position: Hardware Design Engineer, Cisco Systems, Inc., San Jose, CA.
  35. Phil Paik, “Adaptive Hot-Spot Cooling of Integrated Circuits Using Digital Microfluidics”, April 2006; First Position: Senior Design Engineer, Advanced Liquid Logic, Inc., Research Triangle Park, NC.
  36. Fei Su, “Synthesis, Testing, and Reconfiguration Techniques for Digital Microfluidic Biochips”, January 2006; First Position: Senior DFT Engineer, Intel Corporation, Folsom, CA.
  37. Anuja Sehgal, “Test Infrastructure Design for Digital, Mixed-Signal and Hierarchical SOCs”, May 2005; First Position: Senior Design Engineer with AMD Corporation, Sunnyvale, CA. Currently with Nvidia Corporation, San Jose, CA.
  38. Yi Zou, “Coverage-Driven Sensor Deployment and Energy-Efficient Information Processing in Wireless Sensor Networks”, December 2004; First Position: Senior R &D Engineer, Unitrends Software Corporation Columbia , SC. Currently with Intel Corporation, Hillsboro, OR.
  39. Lei Li, “Reducing Test Data Volume for System-on-Chip Integrated Circuits using Test Data Compression and Built-In Self-Test”, August 2004; First Position: Digital Design Engineer with Freescale Semiconductor, Austin, TX.
  40. Ying Zhang, “Dynamic Adaptation for Fault Tolerance and Power Management in Real-Time Embedded Systems”, May 2004; First position: Senior Software Engineer with Guidant Corporation, St. Paul, MN.
  41. Vishnu Swaminathan, “Dynamic Power Management in Hard Real-Time Systems”, May 2003; First position: Researcher at Siemens Corporate Research Center, Bangalore, India.
  42. Chunsheng Liu, “Fault Diagnosis in Scan-BIST with System-on-Chip Applications”, May 2003, First position: Assistant Professor at University of Nebraska. Currently with Nvidia Corporation, San Jose, CA.
  43. Anshuman Chandra, “Test Resource Partitioning and Test Data Compression for System-on-a-Chip”, September 2002; First position: Senior R & D Engineer at Synopsys, Inc., Mountain View, CA.
  44. Vikram Iyengar, “Test Planning and Plug-and-Play Test Automation for System-ona- Chip”, May 2002; First position: Advisory Engineer at IBM Corporation (ASICs Test and Methodology Department), Burlington, VT.
  45. Tianhao Zhang, “An Integrated Hierarchical Modeling and Simulation Approach for Microelectrofluidic Systems”, May 2001 (co-advised with Richard Fair); First position: Senior Member of the Technical Staff at Cadence Design Systems, Research Triangle Park, NC.